View HDSP2113S_200421.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RED YELLOW HIGH EFFICIENCY RED GREEN HIGH EFFICIENCY GREEN
SOFT ORANGE 0.200" 8-Character 5x7 Dot Matrix Parallel Input Alphanumeric Intelligent Display(R) Devices
Dimensions in inches (mm) 1.680 (42.67) max. 0.210 (5.34) 0.105 (2.67) 0.771 (19.58) 0.386 (9.8) Pin 1 Indicator Part Number EIA Date Code HDSP211X SIEMENS WW 0.189 (4.79) 0.018 typ. (.46) Z 1 0.160.020 (4.06.50) 0.012 (0.30) typ. Intensity Code Color Bin (For Yellow Only) 0.209 (5.31) 0.086 (2.19)
HDSP2110S HDSP2111S HDSP2112S HDSP2113S HDSP2114S HDSP2115S
0.189 (4.81)
0.600 (15.24)
FEATURES * Eight 0.200" Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green, High Efficiency Green, or Soft Orange * Built-in 128 Character ROM, Mask Programmable for Custom Fonts * Readable from 8 Feet (2.5 meters) * Built-in Decoders, Multiplexers and Drivers * Wide Viewing Angle, X Axis 55, Y Axis 65 * Programmable Features: - Individual Flashing Character - Full Display Blinking - Multi-Level Dimming and Blanking - Clear Function - Self Test * Internal or External Clock * End Stackable Dual-In-Line Plastic Package * Read/Write Capability * 16 User Definable Characters
0.100 (2.54) typ.
DESCRIPTION The HDSP2110S (Red), HDSP2111S (Yellow), HDSP2112S (High Efficiency Red), HDSP2113S (Green), HDSP2114S (High Efficiency Green), and HDSP2115S (Soft Orange) are eight digit, 5x7 dot matrix, alphanumeric Intelligent Display devices. The 0.20 inch high digits are packaged in a rugged, high quality, optically transparent, 0.6 inch lead spacing, 28 pin plastic DIP. The on-board CMOS has a built-in 128 character ROM. The HDSP211XS also has a user definable character (UDC) feature, which uses a RAM that permits storage of 16 arbitrary characters, symbols or icons that are software-definable by the user. The character ROM itself is mask programmable and easily modified by the manufacturer to provide specified custom characters. The HDSP211XS is designed for standard microprocessor interface techniques, and is fully TTL compatible. The Clock I/O and Clock Select pins allow the user to cascade multiple display modules.
1
ESD Warning:
Standard precautions for CMOS handling should be observed.
Switching specifications (over operating temperature range and VCC=4.5 V) Symbol Tacc Tacc Tacs Tce Tce Tach Tcer Tces Tces Tceh Tw Twd Description Display Access Time--Write Display Access Time--Read Address Setup Time to CE Chip Enable Active Time--Write Chip Enable Active Time--Read Address Hold Time to CE Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge--Write Chip Enable Active Prior to Rising Edge--Read Chip Enable Hold to Rising Edge of Read/Write Signal Write Active Time Data Valid Prior to Rising Edge of Write Signal Data Write Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time Min. 210 230 10 140 160 20 60 140 160 0 100 50 20 160 95 10 300 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns
Maximum Ratings (TA=25C) DC Supply Voltage, VCC to GND (max. voltage with no LEDs on)................... -0.3 to +7.0 VDC Input Voltage Levels, All Inputs........................................................-0.3 to VCC +0.3 Operating Temperature ........................................-40C to 85C Storage Temperature..........................................-40C to 100C Relative Humidity (non-condensing).................................... 85% Operating Voltage, VCC to GND (Max. voltage with 20 dots/digits on)...............................5.5 V Maximum Solder Temperature (0.063" below seating plane, t<5 sec)............................260 C ESD Protection at 1.5 K, 100 pF........................................................VZ=4 KV (each pin) Figure 1. Enlarged character font
Dimensions in inches (mm) 0.112 (2.85) C1 C2 C3 C4 C5 0.030 (0.76) Typ. R1 R2 R3 0.01 (0.254) R4 R5 R6 R7 0.189 (4.81)
Tdh Tr Trd Tdf Trc
0.026 (0.65) Typ.
Figure 2. Write cycle timing diagram
Tacc A0-A3 FL Tach Tacs CE Tces Tw WR Twd D0-D7
Input pulse levels -0.6 V to 2.4 V
Tacs Tcer
Tce
Tceh
Tdh
HDSP2110S/1S/2S/3S/4S/5S
2
Figure 3. Read cycle timing diagram
Tacc A0-A3 FL Tacs CE Tces Tr RD Trd D0-D7 Tdf Tceh Tach Tce Tcer Tacs
Cascading Displays The HDSP211XS oscillator is designed to drive up to 16 other HDSP211XSs with input loading of 15 pF each. The following are the general requirements for cascading 16 displays together: * Determine the correct address for each display. * Use CE from an address decoder to select the correct display. * Select one of the Displays to provide the clock for the other displays. Connect CLKSEL to VCC for this display. * Tie CLKSEL to ground on other displays. * Use RTS to synchronize the blinking between the displays. Figure 4. Cascading diagram
RD WR FL RST VCC RD WR FL RST CLK I/O CLKSEL Display D0-D7 A0-A4
Data I/O Address
RD WR Up to14 More Displays in between
FL
RST CLK I/O CLKSEL Display
CE
D0-D7 A0-A4
CE
A6 A7 A8 A9
0 Address Decoder Address Decode Chip 1 to 14 15
HDSP2110S/1S/2S/3S/4S/5S
3
Optical characteristics at 25C (VCC=5.0 V at full brightness) Red HDSP2110S Description Peak Luminous Intensity Peak Wavelength Dominant Wavelength Yellow HDSP2111S Description Peak Luminous Intensity (1) Symbol IVpeak
(peak) (d)
(1)
Symbol IVpeak
(peak) (d)
Min. 70
Typ. 90 660 639
Units cd/dot nm nm
Min. 130
Typ. 210 583 585
Units cd/dot nm nm
Peak Wavelength Dominant Wavelength High Efficiency Red HDSP2112S Description Peak Luminous Intensity Peak Wavelength Dominant Wavelength Green HDSP2113S Description Peak Luminous Intensity Peak Wavelength Dominant Wavelength High Efficiency Green HDSP2114S Description Peak Luminous Intensity Peak Wavelength Dominant Wavelength Soft Orange HDSP2115S Description Peak Luminous Intensity Peak Wavelength Dominant Wavelength
1)
Symbol
(1)
Min. 150
Typ. 330 630 620
Units cd/dot nm nm
IVpeak
(peak) (d)
Symbol
(1)
Min. 150
Typ. 260 565 570
Units cd/dot nm nm
IVpeak
(peak) (d)
Symbol
(1)
Min. 200
Typ. 510 568 574
Units cd/dot nm nm
IVpeak
(peak) (d)
Symbol
(1)
Min. 150
Typ. 270 610 604
Units cd/dot nm nm
IVpeak
(peak) (d)
Note: Peak luminous intensity is measured at TA=TJ=25C. No time is allowed for the device to warm up prior to measurement.
HDSP2110S/1S/2S/3S/4S/5S
4
Electrical characteristics at 25C Parameters Limits Min. VCC ICC Blank ICC 12 dots/digit on ICC 20 dots/digit on IILP (with pull-up) Input Leakage IIL (no pull-up) Input Leakage VIH Input Voltage High VIL Input Voltage Low VOL (D0-D7), Output Voltage Low VOL (CLK), Output Voltage Low VOH Output Voltage High JC Thermal Resistance, Junction to Case Clock I/O Frequency FM, Digit Multiplex Frequency Blinking Rate Clock I/O Buss Loading Clock Out Rise Time Clock Out Fall Time 28 125 0.98 2.4 25 57.34 256 2.0 81.14 362.5 2.83 2.40 500 500
(1) (2) (1) (2)
Conditions Typ. 5.0 0.65 185 284 Max. 5.5 1.0 255 370 -5 Units V mA mA mA A A V V 0.4 0.4 V V V C/W KHz Hz Hz pF nsec nsec VCC=4.5 V, VOH=2.4 V VCC=4.5 V, VOH=0.4 V VCC=4.5 to 5.5 V VCC=4.5 to 5.5 V VCC=5 V, VIN=5 V VCC=5 V, "V" in all 8 digits VCC=5 V, "#" in all 8 digits VCC=5 V, VIN=0 V to VCC, (WR, CE, FL, RST, RD, CLKSEL) VCC=5 V, VIN=0-5 V, (CLK, A0-A3, D0-D7) VCC=4.5 V to 5.5 V VCC=4.5 V to 5.5 V VCC=4.5 V, IOL=1.6 mA VCC=4.5 V, IOL=40 A VCC=4.5 V, IOH=-40 A
4.5
-18
-11
-1 2.0 GND -0.3
+1 VCC +0.3
Notes: 1) I CC is an average value. 2) I 28 CC is measured with the display at full brightness. Peak ICC= /15 ICC average (#displayed).
Recommended operating conditions (TA=-40C to +85C) Parameter Supply Voltage Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Symbol VCC VIL VIH VOL VOH 2.4 2.0 0.4 Min. 4.5 Max. 5.5 0.8 Units V V V V V
HDSP2110S/1S/2S/3S/4S/5S
5
Figure 5. Top view
28 Pins 15
Pin assignment (continued) Pin 12 13 Function CLK I/O WR VCC GND supply GND logic CE RD Definition Outputs master clock or inputs external clock A low will write data into the display if CE is low Positive power supply input Analog Ground for LED drivers Digital Ground for internal drivers Enables access to the display A low will read data from the display if CE is low. If read from display is not required, then RD can be tied to VCC Data input LSB Data input
0
1
2
3 Digit
4
5
6
7
14
14
1
Pins
15 16
Pin assignment Pin 1 Function RST Definition Used to initialize a display and sychronize blinking for multiple displays Low input accesses the Flash RAM Address input LSB Address input Address input MSB Mode selector Optional connection to positive power supply input. Mode Selector Selects internal/high clock source
17 18
2 3 4 5 6 7 8 9 10 11
FL A0 A1 A2 A3 VCC VCC VCC A4 CLKSEL
19 20 21 22 23 24 25 26 27 28
D0 D1 No pin No pin D2 D3 D4 D5 D6 D7
Data input Data input Data input Data input Data input Data input MSB, selects ROM, page 1 or 2
Figure 6. Character set
D0 D1 D2 D3 D7 D6 D5 D4 HEX ASCII CODE L L L L 0 L L L L 0 H L L L 1 L H L L 2 H H L L 3 L L H L 4 H L H L 5 L H H L 6 H H H L 7 L L L H 8 H L L H 9 L H L H A H H L H B L L H H C H L H H D L H H H E H H H H F
Notes: 1. Upon power up, the device will initialize in a random state. 2. X=don't care.
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
X
X
X
8
UDC UDC 0 1
UDC UDC UDC UDC 2 3 4 5
UDC UDC 6 7
UDC UDC 8 9
UDC UDC 10 11
UDC 12
UDC 13
UDC 14
UDC 15
HDSP2110S/1S/2S/3S/4S/5S
6
Figure 7. Block diagram
OSC
/32 Counter
/7 Counter
Row Drivers
8 Digit Display
Column Drivers
/128 Counter
/3 Counter
Character RAM Decode
Character RAM
D Latch Holding Register
ROM 64 Word Decode
ROM
5
Column Latch S M l a a s t 25 v e e r
25
Cursor Controls and Display MUX
Character Decode 16 for Display
5
16 Data Bus 4 UDC Address Register 4 Character Decode
(Read/Write)
UDC RAM
Self Test
Control Word Register
Flash RAM
Functional Description The display's user interface is organized into five memory areas. They are accessed using the Flash Input, FL, and address lines, A3 and A4. All the listed RAMs and Registers may be read or written through the data bus. See Table 1. Each input pin is described in Pin Definitions. Five basic memory areas Character RAM Stores either ASCII (Katakana) character data or an UDC RAM address 1x8 RAM which stores Flash data Stores dot pattern for custom characters Provides address to UDC RAM when user is writing or reading custom character Enables adjustment of display brightness, flash individual characters, blink, self test or clearing the display RST can be used to initialize display operation upon power up or during normal operation. When activated, RST will clear the Flash RAM and Control Word Register (00H) and reset the internal counter. All eight display memory locations will be set to 20H to show blanks in all digits. FL pin enables access to the Flash RAM. The Flash RAM will set (D0=1) or reset (D0=0) flashing of the character addressed by A0-A2. The 1x8 bit Control Word Register is loaded with attribute data if A3=0. The Control Word Logic decodes attribute data for proper implementation. Character ROM is designed for 128 ASCII characters. The ROM is Mask Programmable for custom fonts. The Clock Source could either be the internal oscillator (CLKSEL=1) of the device or an external clock (CLKSEL=0) could be an input from another HDSP211X display for the synchronization of blinking for multiple displays. The Display Multiplexer controls the Row Drivers so no additional logic is required for a display system. The Display has eight digits. Each digit has 35 LEDs clustered into a 5x7 dot matrix.
Flash RAM User-Defined Character RAM (UDC RAM) User-Defined Address Register (UDC Address Register) Control Word Register
HDSP2110S/1S/2S/3S/4S/5S
7
Table 1. Memory selection FL 0 1 1 1 1 A2 X 0 0 1 1 A3 X 0 1 1 0 Section of Memory Flash RAM UDC Address Register UDC RAM Character RAM Control Word Register A2-A0 Character Address Don't Care Row Address Character Address Don't Care Data Bits Used D0 D3-D0 D4-D0 D7-D0 D7-D0
Theory of operation The HDSP211XS Programmable Display is designed to work with all major microprocessors. Data entry is via an eight bit parallel bus. Three bits of address route the data to the proper digit location in the RAM. Standard control signals like WR and CE allow the data to be written into the display. D0-D7 data bits are used for both Character RAM and control word data input. A3 acts as the mode selector. If A3=1, character RAM is selected. Then input data bit D7 will determine whether input data bits D0-D6 is ASCII coded data (D7=0) or UDC data (D7=1). See section on UDC Address Register and RAM. For normal operation FL pin should be held high. When FL is held low, Flash RAM is accessed to set character blinking. The seven bit ASCII code is decoded by the Character ROM to generate Column data. Twenty columns worth of data is sent out each display cycle, and it takes fourteen display cycles to write into eight digits. The rows are multiplexed in two sets of seven rows each. The internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. Power Up Sequence Upon power up display will come on at random. Thus the display should be reset on power-up. The reset will clear the Flash RAM, Control Word Register and reset the internal counter. All the digits will show blanks and display brightness level will be 100%. The display must not be accessed until three clock pulses (110 seconds minimum using the internal clock) after the rising edge of the reset line. Microprocessor interface The interface to a microprocessor is through the 8-bit data bus (D0-D7), the 4-bit address bus (A0-A3) and control lines FL, CE and WR. To write data (ASCII/Control Word) into the display CE should be held low, address and data signals stable and WR should be brought low. The data is written on the low to high transition of WR. The Control Word is decoded by the Control Word Decode Logic. Each code has a different function. The code for display brightness changes the duty cycle for the column drivers. The peak LED current stays the same but the average LED current diminishes depending on the intensity level. The character Flash Enable causes 2 Hz coming out of the counter to be ANDED with column drive signal and makes the column driver to cycle at 2 Hz. Thus the character flashes at 2 Hz. The display Blink works the same way as the Flash Enable but causes all twenty column drivers to cycle at 2 Hz thereby making all eight digits to blink at 2 Hz. The Self Test function of the IC consists of two internal routines which exercise major portions of the IC and illuminates all the LEDs. Clear bit clears the character RAM and writes a blank into the display memory. It however does not clear the control word. ASCII Data or Control Word Data can be written into the display at this point. For multiple display operation, CLK I/O must be properly selected. CLK I/O will output the internal clock if CLKSEL=1, or will allow input from an external clock if CLKSEL=0. Character RAM The Character RAM is selected when FL, A4 and A3 are set to 1,1,1 during a read or write cycle. The Character RAM is a 8 by 8 bit RAM with each of the eight locations corresponding to a digit on the display. Digit 0 is on the left side of the display and digit 7 is on the right side of the display. Address lines, A2-A0 select the digit address with A2 being the most significant bit and A0 being the least significant bit. The two types of data stored in the Character RAM are the ASCII coded data and the UDC Address Data. The type of data stored in the Character RAM is determined by data bit, D7. If D7 is low, then ASCII coded data is stored in data bits D6-D0. If D7 is high, then UDC Address Data is stored in data bit D3-D0. The ASCII coded data is a 7 bit code used to select one of 128 ASCII characters permanently stored in the ASCII ROM. The UDC Address data is a 4 bit code used to select one of the UDC characters in the UDC RAM. There are up to 16 characters available. See Figure 8. UDC Address Register and UDC RAM The UDC Address Register and UDC RAM allows the user to generate and store up to 16 custom characters. Each custom character is defined in 5x7 dot matrix pattern. It takes 8 write cycles to define a custom character, one cycle to load the UDC Address Register and 7 cycles to define the character. The contents of the UDC Address Register will store the 4 bit address for one of the 16 UDC RAM locations. The UDC RAM is used to store the custom character.
HDSP2110S/1S/2S/3S/4S/5S
8
UDC Address Register The UDC Address Register is selected by setting FL=1, A4=0, A3=0. It is a 4 bit register and uses data bits, D3-D0 to store the 4 bit address code (D7-D4 are ignored). The address code selects one of 16 UDC RAM locations for custom character generation. UDC RAM The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM is comprised of a 7x5 bit RAM. As shown in Figure 11, address lines, A2-A0 select one of the 7 rows of the custom character. Data bits, D4-D0 determine the 5 bits of column data in each row. Each data bit corresponds to a LED. If the data bit is high, then the LED is on. If the data bit is low, the LED is off. To create a character, each of the 7 rows of column data need to be defined. See Figures 9 and 10 for logic. Flash RAM The Flash RAM allows the display to flash one or more of the characters being displayed. The Flash Ram is accessed by setting FL low. A4 and A3 are ignored. The Flash RAM is a 8x1 bit RAM with each bit corresponding to a digit address. Digit 0 is on the left side of the display and digit 7 is on the right side of the display. Address lines, A2-A0 select the digit address with A2 being the most significant digit and A0 being the least significant digit. Data bit, D0, sets and resets the flash bit for each digit. When D0 is high, the flash bit is set and when D0 is low, It is reset. See Figure 11. Figure 8. Character RAM access logic RST 1 1 1 1 CE 0 0 0 0 WR 0 1 0 1 RD 1 0 1 0 FL 1 1 1 1 A4 1 1 0 0 A3 1 1 0 0 A2 A1
Control Word The Control Word is used to set up the attributes required by the user. It is addressed by setting FL=1, A4=1, A3=0. The Control Word is an 8 bit register and is accessed using data bits, D7-D0. See Figures 12 and 13 for the logic and attributed control. The Control Word has 5 functions. They are brightness control, flashing character enable, blinking character enable, self test, and clear (Flash and Character RAMS only). Brightness Control Control Word bits, D2-D0, control the brightness of the display with a binary code of 000 being 100% brightness and 111 being display blank. See Figure 13 for brightness level versus binary code. The average ICC can be calculated by multiplying the 100% brightness level ICC value by the display's brightness level. For example, a display set to 80% brightness with a 100% average ICC value of 200 mA will have an average ICC value of 200 mA x 80%=160 mA. Flash Function Control Word bit, D3, enables or disables the Flash Function. When D3 is 1, the Flash Function is enabled and any digit with its corresponding bit set in the Flash RAM will flash at approximately 2 Hz. When using an external clock, the flash rate can be determined by dividing the clock rate by 28,672. When D3 is 0, the Flash Function is disabled and the contents of the Flash RAM is ignored. For synchronized flashing on multiple displays, see the Reset Section.
A0
D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 7 bit ASCII code for a Write Cycle 7 bit ASCII code read during a Read Cycle D3-D0=UDC address for a Write Cycle D3-D0=UDC address for Read Data
Character Address for Digits 0-7 Character Address for Digits 0-7 Character Address for Digits 0-7 Character Address for Digits 0-7
Figure 9. UDC address register and UDC character RAM RST 1 1 1 1 CE 0 0 0 0 WR 0 1 0 1 RD 1 0 1 0 FL 1 1 1 1 A4 0 0 0 0 A3 0 0 1 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D3-D0=UDC RAM Address Code for Write Cycle D3-D0=UDC RAM Address Code for Read Cycle D4-D0=Character Column Data for Write Cycle D4-D0=Character Column Data read during a Read Cycle UDC Address Register
Not used for UDC Address Register Not used for UDC Address Register A2-A0=Character Row Address A2-A0=Character Row Address
UDC RAM
HDSP2110S/1S/2S/3S/4S/5S
9
Blink Function Control Word bit, D4, enables or disables the Blink Function. When D4 is 1, the Blink Function is enabled and all characters on the display will blink at approximately 2 Hz. The Blink Function will override the Flash Function if both functions are enabled. When D4 is 0, the Blink Function is disabled. When using an external clock, the blink rate can be determined by dividing the clock rate by 28,672. For synchronized blinking on multiple displays, see the Reset Section. Self Test Before starting Self Test, Reset must first be activated. Control Word bits, D6 and D5, are used for the Self Test Function. When D6 is 1, the Self Test is initiated. Results of the Self Test are stored in bits D5. Control Word bit, D5, is a read only bit. When D5 is 1, Self Test passed is indicated. When D5 is 0, Self Test failed is indicated. The Self Test function of the IC consists of two internal routines which exercise major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a check sum on the output. If the check sum agrees with the correct value, D5 is set to a 1. Figure 10. UDC character map Row Data Column Data C1 A2 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 Row # 1 2 3 4 5 6 7 5x7 Dot Matrix Pattern D4 C2 D3 C3 D2 C4 D1 C5 D0
The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock time by 262,144 (typical time 4.6 sec.). At the end of the self test function, the Character RAM is loaded with blanks; the Control Word Register is set to zeroes except D5, and the Flash RAM is cleared and the UDC Address Register is set to all 1s. Clear Function (see Figures 13 and 14) Control Word bit, D7 clears the character RAM to 20 hex and the flash RAM to all zeroes. The RAMs are cleared within three clock cycles (110 s minimum, using the internal clock) when D7 is set to 1. During the clear time the display must not be accessed. When the clear function is finished, bit 7 of the Control Word RAM will be reset to a "0". Reset Function The display should be reset on power up of the display (RST=LOW). When the display is reset, the Character RAM, Flash RAM, and Control Word Register are cleared. The display's internal counters are reset. Reset cycle takes three clock cycles (110 seconds minimum using the internal clock). The display must not be accessed during this time. To synchronize the flashing and blinking of multiple displays, it is necessary for the display to use a common clock source and reset all the displays at the same time to start the internal counters at the same place. While RST is low, the display must not be accessed by RD nor WR.
Figure 11. Flash RAM access logic RST 1 1 CE 0 0 WR 0 1 RD 1 0 FL 0 0 A4 X X A3 X X A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D0=Flash Data, 0-Flash Off and 1=Flash On (Write Cycle) D0=Flash Data, 0-Flash Off and 1=Flash On (Read Cycle)
Flash RAM Address for Digits 0-7 Flash RAM Address for Digits 0-7
Figure 12. Control word access logic RST 1 1 CE 0 0 WR 0 1 RD 1 0 FL 1 1 A4 1 1 A3 0 0 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Control Word data for a Write Cycle, see Figure 13 Control Word data for a Read during a Read Cycle
Not used for Control Word Not used for Control Word
HDSP2110S/1S/2S/3S/4S/5S
10
Figure613. Control word data definition Fig
D7 C D6 ST D5 ST D4 BL D3 FL D2 Br 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 X R D1 Br 0 0 1 1 0 0 1 1 D0 Br 0 1 0 1 0 0 0 1 100% Brightness 80% Brightness 53% Brightness 40% Brightness 27% Brightness 20% Brightness 13% Brightness Blank Display
Key C ST BL FL Br Clear Function Self test Blink function Flash function Brightness control
Flash Function Disabled Flash Function Enabled
Blink Function Disabled Blink Function Enabled (overrides Flash Function)
Normal Operation X=bit ignored Run Self Test, R=Test Result, R=1/pass, 0=fail
Normal Operation Clear Flash RAM & Character RAM (Character RAM=20 Hex)
Figure 14. Clear function CE 0 0 WR 0 0 FL 1 1 A3 0 0 A2 X X A1 X X A0 X X D7 0 1 D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 X X Operation Clear disabled Clear user RAM, page RAM, flash RAM and display
X=don't care
Figure 15. Display cycle using built-in ROM example Display message "Showtime." Digit 0 is leftmost--closest to pin 1. Logic levels: 0=Low, 1=High, X=Don't care. RST CE 0 1 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0 WR RD 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 FL 1 1 1 1 1 1 1 1 1 1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation X 1 1 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 1 X X 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X 0 0 0 0 0 0 0 0 0 X 0 1 1 1 1 1 1 1 1 X X 0 0 0 0 0 0 0 0 X 0 1 0 0 1 1 0 0 0 X 0 0 1 1 0 0 1 1 0 X 0 0 0 1 1 1 0 1 1 X 1 1 0 1 1 0 0 0 0 X 1 1 0 1 1 0 1 1 1 Reset. No Read/Write Within 3 Clock Cycles 53% Brightness Selected Write "S" to Digit 0 Write "H" to Digit 1 Write "O" to Digit 2 Write "W" to Digit 3 Write "T" to Digit 4 Write "I" to Digit 5 Write "M" to Digit 6 Write "E" to Digit 7 Display All Blank All Blank S SH SHO SHOW SHOWT SHOWTI SHOWTIM SHOWTIME
HDSP2110S/1S/2S/3S/4S/5S
11
Figure 16. Displaying user defined character example Load character "A" into UDC-5 and then display it in digit 2 Logic levels: 0=Low, 1=High, X=Don`t care RST CE 0 1 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0 WR RD 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 FL 1 1 1 1 1 1 1 1 1 1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation X 0 0 0 0 0 0 0 0 1 X 0 1 1 1 1 1 1 1 1 X X 0 0 0 0 1 1 1 0 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 0 X X X X X X X X X 1 X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 1 1 1 X X 0 1 0 0 1 0 0 0 0 X 1 1 0 0 1 0 0 0 1 X 0 1 0 0 1 0 0 0 0 X 1 0 1 1 1 1 1 1 1 Reset. No Read/Write Within 3 Clock Cycles Select UDC-5 Write into Row 1 of UDC-5 Write into Row 2 of UDC-5 Write into Row 3 of UDC-5 Write into Row 4 of UDC-5 Write into Row 5 of UDC-5 Write into Row 6 of UDC-5 Write into Row 7 of UDC-5 Write UDC-5 into Digit 2 Display All Blank All Blank All Blank All Blank All Blank All Blank All Blank All Blank All Blank (Digit 2) A
Electrical and Mechanical Considerations Voltage Transient Suppression For best results power the display and the components that interface with the display to avoid logic inputs higher than VCC. Additionally, the LEDs may cause transients in the power supply line while they change display states. The common practice is to place a parallel combination of a .01 F and a 22 F capacitor between VCC and GND for all display packages. ESD Protection The input protection structure of the HDSP211XS provides significant protection against ESD damage. It is capable of withstanding discharges greater than 2 KV. Take all the standard precautions, normal for CMOS components. These include properly grounding personnel, tools, tables, and transport carriers that come in contact with unshielded parts. If these conditions are not, or cannot be met, keep the leads of the device shorted together or the parts in antistatic packaging. Soldering Considerations The HDSP211XS can be hand soldered with SN63 solder using a grounded iron set to 260C. Wave soldering is also possible following these conditions: Preheat that does not exceed 93C on the solder side of the PC board or a package surface temperature of 85C. Water soluble organic acid flux (except carboxylic acid) or resin-based RMA flux without alcohol can be used. Direct contact with alcohol or alcohol vapor will cause degradation of the package. Wave temperature of 245C 5C with a dwell between 1.5 sec. to 3.0 sec. Exposure to the wave should not exceed temperatures above 260C for five seconds at 0.063" below the seating plane. The packages should not be immersed in the wave.
Post Solder Cleaning Procedures The least offensive cleaning solution is hot D.I. water (60C) for less than 15 minutes. Addition of mild saponifiers is acceptable. Do not use commercial dishwasher detergents. For faster cleaning, solvents may be used. Exercise care in choosing solvents as some may chemically attack the nylon package. Maximum exposure should not exceed two minutes at elevated temperatures. Acceptable solvents are TF (trichorotrifluorethane), TA, 111 Trichloroethane, and unheated acetone.(1)
Note: 1) Acceptable commercial solvents are: Basic TF, Arklone, P. Genesolv, D. Genesolv DA, Blaco-Tron TF, Blaco-Tron TA, and Freon TA.
Unacceptable solvents contain alcohol, methanol, methylene chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since many commercial mixtures exist, contact a solvent vendor for chemical composition information. Some major solvent manufacturers are: Allied Chemical Corporation, Specialty Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilmington, DE. For further information refer to Appnotes 18 and 19 in the current Siemens Optoelectronic Data Book. An alternative to soldering and cleaning the display modules is to use sockets. Naturally, 28 pin DIP sockets .600" wide with .100" centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or DIP sockets when available for uniform package alignment. Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec Electronic Hardward, New Albany, IN. For further information refer to Appnote 22 in the current Siemens Optoelectronic Data Book.
HDSP2110S/1S/2S/3S/4S/5S
12
Optical Considerations The .200" high character of the HDSP211XS gives readability up to eight feet. Proper filter selection enhances readability over this distance. Using filters emphasizes the contrast ratio between a lit LED and the character background. This will increase the discrimination of different characters. The only limitation is cost. Take into consideration the ambient lighting environment for the best cost/benefit ratio for filters. Incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. Plastic band-pass filters are an inexpensive and effective way to strengthen contrast ratios. The HDSP2110/2112S are red/high efficiency red displays and should be matched with long wavelength pass filter in the 570 nm to 590 nm range. The HDSP2113S should be matched with a yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compromise. Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next step up in contrast improvement. Plastic filters can be improved further with anti-reflective coatings to reduce glare. The trade-off is fuzzy characters. Mounting the filters close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow. Optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. The circular polarizing further enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%. Several filter manufacturers supply quality filter materials. Some of them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics, Inc., Fremont, CA. One last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead lighting situations. Several bezel manufacturers are: R.M.F. Products, Baklava, IL; Nobody Components, Griffith Plastic Corp., Burningly, CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.
HDSP2110S/1S/2S/3S/4S/5S
13

▲Up To Search▲

Price & Availability of HDSP2113S

	To Download HDSP2113S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .